This invention relates generally to a semiconductor memory device, and more specifically to a technique which is effective when applied to an electrically erasable Read Only Memory (ROM) device whose memory cells each consist of MISFET having a floating gate electrode and a control gate electrode, that is an EEPROM (Electrically Erasable and Programmable ROM).
Each memory cell of an EEPROM consisting of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a floating gate electrode and a control gate electrode is described, for example, in 1984 "International Electron Devices Meeting, Technical Digest", pp 468-471.
In the memory cell described above, a strong electric field of higher than 10 MV/cm is applied to a thin oxide film below a floating gate in order to cause tunnel injection of electrons into the floating gate from a substrate through the thin oxide film to cause tunnel emission of the electrons into the substrate from the floating gate. The overlap area between the floating gate and a control gate of the memory cell must be large enough for tunneling the electrons sufficiently to write or erase the information to and from the memory cell. The memory cell consists of two elements, that is, a memory transistor and a select transistor. For these reasons, the memory cell is about five times greater in size than the memory cell of an EPROM having the same floating gate and control gate.
To reduce the cell size, therefore, a one-element type memory cell having a floating gate electrode and a control gate electrode has been proposed (1985 International Electron Devices Meeting, Technical Digest, pp. 616-619). In this memory cell, injection (write) of the electrons into the floating gate is made by the injection of hot electrons generated at the edge of a drain region while emission (erase) of the electrons from the floating gate is made by tunnel emission into a source region.